1. Field of the Invention
The present invention relates to a method for upgrading qualities of dynamic random access memories (DRAM) and more particularly to a method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity.
2. Description of the Related Art
A capacitor is a key component of a dynamic random access memory (DRAM) device. Especially, the quality of a DRAM device does strongly depend on performance of the capacitor. In addition, as the DRAM fabrication technology achieves the deep sub-micron level, it is a crucial issue to reduce the dimension of a DRAM device, meanwhile, increase the capacitance without degrading the quality.
Currently, there are two main considering points to improve capacitance with reduced dimension. One is using a dielectric material with high dielectric constant K, and the other one is increasing the capacitor surface. The dielectric material with high dielectric constant includes, for example, tantalum oxide (Ta2O5) with K about equal to 25 or barium titanate (BaTiO3) with K even as high as about 1000. About the solution of increasing the capacitor surface, there are also two main methods. The two types of formed capacitors are called a deep-trench type and a stack type respectively. The deep-trench capacitor typically includes a trench with a depth of about 6-7 microns. After filling the deep trench with a dielectric material, a deep-trench capacitor is formed. The deep-trench capacitor can have a large capacitance but it is difficult to be formed. The stack-type capacitor is the main type for the current fabrication trend since the stack-type capacitor has many advantages, for example, the high capacitance and the well-performed manufacturing technique.
The hemispherical grains (HSG) and the selective hemispherical grains (SHSG) technologies play a major role in modern DRAM manufacturing processes. FIG. 1A shows a cross-sectional view of a conventional stack-type capacitor. As shown in FIG. 1A, a SHSG layer 108 of the capacitor is formed by using the SHSG method. For better understanding, a substrate 100, a conductive plug 102, a dielectric layer 104, an amorphous silicon layer 106, a dielectric layer 110, and a conductive layer 112 served as the upper electrode are also shown in FIG. 1A. The SHSG layer 108 is formed by performing a seeding process in a ultra high vacuum (UHV) environment with gas of silane (SiH4) or disilane (Si2H6) and a thermal process in situ.
FIG. 1B shows a time vs. temperature diagram of a conventional SHSG seeding process. Steps of loading wafers and sequentially heating the wafers are indicated by line 10. Line 12 represents serial steps of sealing the UHV reactor, performing about 12 cycles of helium purge process, and heating the wafers to a temperature of a SHSG seeding reaction. Line 14 indicates the SHSG seeding stage. It is noted that the seeding process requires an environment of an extremely high purity, but various contaminants always exist. Typical contaminants, for example, oxygen and organics, appear apparently when wafers are heated up. In order to prevent contaminations from wafer outgassing, Helium (He) gas flows are previously introduced into the chamber of a UHV system before performing the SHSG seeding process. However, as a matter of fact, the He purge process is still unable to remove the contamination source effectively. For example, it is found that capacitance values of capacitors on wafers located near the upper end of a vertical furnace or chamber of a UHV reactor are often lower. The yield ratio of the DRAM devices thus cannot be improved further. Two possible reasons are the pump position of the UHV reactor and the inertia of He gas. That is, the ultra high vacuum pump is usually disposed bn the bottom end of the UHV reactor and the noble He gas cannot react with the contaminants. In view of the issue mentioned above, it is very necessary to provide a solution to improve the yield ratio and lower the cost of the DRAM device manufacture. The invention used an additional silane purge process in situ is just the answer.
It is therefore an object of the invention to provide a method for upgrading qualities of DRAM capacitors by effectively removing contaminants appeared in an UHV reactor in a SHSG seeding process.
It is another object of this invention to improve the yield ratio of the DRAM devices and the wafer-to-wafer capacitance uniformity.
It is a further object of this invention to lower the cost of the DRAM device manufacture.
It is still another object of this invention to provide a convenient and high efficient purge process.
To achieve these objects, and in accordance with the purpose of the invention, the invention use an additional silane purge process in situ to effectively purge out potential contamination sources amid a conventional SHSG seeding process. First of all, wafers having semifinished DRAM therein are loaded. Then the wafers are transferred into a reactor chamber of an ultra high vacuum process module.
Furthermore, the wafers are heated. Then the reactor chamber is sealed. Then a silane purge cycle comprising introducing and extracting a silane gas is performed in the reactor chamber for several times. Moreover, a helium purge cycle comprising introducing and extracting a helium gas is performed for several times in situ. Finally, a seeding process is performed on the wafers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.